As part of your role, you will integrate state-of-the-art design-for-test techniques and use industry-standard IP blocks to ensure the functionality and testability of our chips. * You will perform comprehensive HDL checks (LINT, consistency, CDC), create floorplans for RF components, and integrate hard macro designs into higher-level hierarchies. * Additionally, you will take ownership of sign-off verification, including Static Timing Analysis (STA), Electromigration (EM), IR-drop analysis, Equivalence Checking (EC), and gate-level simulation, to ensure the quality of our designs. * Experience and Knowledge: solid knowledge of digital ASIC design, IP integration, digital layout, RTL-to-GDS flow, UPF and verification; experience in the development of analog RF SoCs for automotive applications, includi
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